IBM unveils sub-1-nanometer chip architecture that stacks 100 billion transistors onto a fingernail-sized processor

IBM unveils sub-1-nanometer chip architecture that stacks 100 billion transistors onto a fingernail-sized processor

Rather than continuing to shrink components along a flat plane, IBM is stacking transistors vertically. That change comes as semiconductor designers run up against the physical limits of traditional scaling, making further miniaturization increasingly difficult and less efficient.

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